A process of manufacturing microelectronic circuit packages without the use of commoning bars is provided, specifically the manufacture of flexible wiring boards having a nickel/gold wirebonding surface on wirebond and ball grid array pads is described.
To facilitate the understanding of this specification and the appended claims, definitions to various words and phrases are provided;
Componentxe2x80x94a functional unit that is attached to a printed wiring board package either through a surface mounting or through hole,
Elementxe2x80x94a functional unit integrally associated with the substrate of a printed wiring board (e.g., features and microcircuitry),
Featuresxe2x80x94Elements other than microcircuitry that are an integral part of the substrate of a printed wiring board (e.g., planar resistors, pads, lands, and commoning bar),
Landsxe2x80x94an SMT feature used for electrically interconnecting a component to a printed wiring board,
Microcircuitry (or fine-line circuitry)- electrically conductive lines that carry I/O signals, power, or create a path to ground,
Nascentxe2x80x94yet to be formed (e.g., in the process of manufacturing discrete microcircuitry, at early stages in the process the metallized microcircuits are formed but still are electrically attached to one another, at these stages the microcircuits are still in nascent form),
SMTxe2x80x94surface mount technology, and
VLSIxe2x80x94very large scale integrated circuit.
In the past decade the density per unit area of electronic devices, such as VLSIs, has greatly increased. By some estimates this increase in density has been on the order of 10,000 times what it was in the earliest days of the technology. The space or area available outside of a VLSI in which to make the large number of necessary connections to and from it and to provide the necessary circuitry is becoming almost vanishingly small measured by previous standards.
Electronic circuits, and more particularly the more complex circuits found in computer logic systems, frequently employ one or more printed circuit or wiring boards on which various components or elements are mounted. Unlike the density increase of VLSIs, however, the density of passive circuits on printed wiring boards have increased by only a relatively small factor: less than about 4 to 1 as the components have not decreased in size significantly. This presents the difficult problem of providing circuitry on the printed wiring board which is small enough to fit the spaces available and which is also sufficiently reliable and manufacturable to be economically useful.
With this ever-continuing trend toward reduced size of electronic components and the resulting need for high density requirements in electronic packaging, there has been an increased demand to create a metallization process that will efficiently generate high quality, high density electronic packaging such as printed wiring board structures.
In order to electronically interconnect components and printed circuit boards for feeding electrical power and signals to the circuit elements and for extracting signals therefrom, various connector arrangements are utilized. Components of the external system can be integrated circuit chips, adapter cards, and insulating packages. The leads of these components are in the form of pads on the surface or other contacts extending therefrom in rows to form planar disposed arrays matched with conductive pads on circuits joined to circuit traces leading to and from the components.
Interconnection between the conductive pads or leads of a component to the conductive pads or traces of a circuit board is accomplished in a number of ways, including solder or, in instances where the removal and replacement of components is necessary during the life of a system, by some suitable electrical connector or disconnect. In the latter case, electrical connection between printed circuit boards and cards and external systems can be provided by gold contacts such as edge tabs, chip tabs, and lands. The gold contacts atop lands and tabs are typically provided by electrodeposition.
Electroplating is one method of depositing an adherent metal coating on a substrate for protection purposes. The substrate to be plated is connected to one terminal of d.c. or a pulsed plating voltage source and placed in an electrolyte. The metal to be deposited is connected to the other terminal and similarly immersed in the electrolyte. The transfer of the metal is accomplished via the ions contained in the current flowing between the electrodes.
Electroless plating is another method of depositing a metal. It involves the use of a plating bath without the imposition of any electric current. The substrate is plated by reduction of a plating metal from a solution of a salt of the plating metal. The plating solution contains controlled reducing agents which are generally catalyzed either by the surface of the substrate, or by some catalytic metal placed onto the surface both to initiate the reduction and to render good adherence. Since the plated-on surface is autocatalytic, an electroless process can be used to build up thicknesses.
Electrodeposition (electroplating) of gold has been the preferred method for plating gold, since the deposited gold has improved physical properties (e.g., less brittle) compared to electroless plated gold. This softness or plasticity is desirable in order to provide contact sites with high durability, especially where components can be replaced multiple times or wire bonding is required. The plasticity of electroplated gold also assists in ameliorating the brittleness of an electroless plated nickel or nickel/phosphorous layer that is optionally plated between the conductive copper features and the gold, or other precious metal overplating. However, a major disadvantage with electrolytic gold plating is the need for commoning bars to provide electrical connections to the features to be plated. These commoning bars require fairly large footprints on the printed wiring board, ultimately wasting valuable space that could otherwise be used for placement of additional circuitry or other features such as planar resistors, capacitors, inductors, diodes, or transistors.
As previously mentioned, numerous types and varieties of modern equipment and devices require sophisticated interconnection of electronic components. With the constant demand for reduced sizes in electronic components and the resulting high density of conductive interconnection surfaces on such equipment, there have been increased demands on the performance of contacts used to provide such interconnections.
A conventional pin and socket connector part, such as a 25 square metal wire-wrap post, has sufficient size and strength to permit it to be made and handled easily with conventional techniques. Typically parts of such xe2x80x9clargexe2x80x9d size are assembled into connector systems having xe2x80x9clargexe2x80x9d centers, such as one-tenth by one-tenth inch. But connectors this large and unwieldy are like the dinosaurs of a past age in the environment of the VLSIs of today. As interconnections are made smaller and smaller, the problems associated with manufacturing and assembling these miniature parts seem to grow exponentially.
Printed circuits are normally formed on boards or laminate sheets made of various epoxy compositions or fiberglass and relatively thin layers of copper which have been etched or deposited to define the desired circuit. The problem in each case is one of coupling interconnections from the relatively thin circuit conductor leads which are xe2x80x9cprintedxe2x80x9d on the board to either a solder site or a mechanical connector which is generally three-dimensional. In the past, these boards or sheets were rigid substrates; but due to the desire to further reduce the size and weight of the passive circuitry and the added benefit of having the design of higher level packaging where planarity was no longer a restriction, the use of lightweight and flexible materials is advantageous. In turn, the trend toward flexible substrates requires the potential reoptimization of the interconnections and circuitry on the substrate due to changes in forces (i.e., bending forces) from directions not originally encountered in the rigid substrates. These bending forces have impact especially at interfaces between the components and the precious metal plated surface mounting on the substrate. Typically, the impact of these bending forces is detrimental to the adhesion between these components and their surface mountings.
Flexible film packages are generally similar to pre-preg based circuit packages but are thinner and are fabricated from polyimides, polyesters or the like rather than epoxy-glass fiber. Flex packaging is described by Donald P. Seraphim, Donald E. Barr, William T. Chen, George P. Schmitt, and Rao R. Tummala in Printed Circuit Board Packaging, at pages 853-921; on pages 870-872 of R. R. Tummala and E. J. Rymaszewski, Microelectronics Packaging Handbook, and also in Flexible Circuit Technology by Joseph Fjelstad (Silicon Valley Publishing Group) and Flexible Printed Circuitry by Thomas Stearns (McGraw-Hill Publishers, February 1996). These references are incorporated by reference to provide general background information on the processes and materials as known in the art as they correspond to the present invention.
The process of surface circuitization of flex packages, as described in the three references cited above, is typically begun by bonding copper foil with a suitable adhesive, such as epoxy or acrylic, and photolithographically patterning the copper into circuit leads. Subsequent processing of polymeric substrates includes circuitization; that is, the formation of a Cu signal pattern or power pattern on the prepreg or flexible support, or lamination of the prepreg to a power core.
Circuitization may be additive or subtractive. In the case of additive circuitization a thin adhesion layer, such as a thin film of chromium, is first applied to the flexible support. The adhesion layer may be applied by various techniques such as sputtering, evaporation, deposition, or wet seeding using palladium colloids. Typically, the film of adhesion metal is from about 50 Angstroms to about 500 Angstroms in thickness. Thicker layers of chromium result in internal stresses, while thinner layers may be non-continuous.
Thereafter a xe2x80x9cseedxe2x80x9d layer of copper is applied atop the adhesion layer. This copper seed layer is from about 1,500 Angstroms to about 50,000 Angstroms thick. It may be applied by sputtering, evaporation, electrodeposition, or electroless deposition.
Subsequently, photoresist is applied atop the copper seed layer, imaged, and developed to provide a pattern for circuit deposition. Copper circuitization is then plated onto the seed layer to provide the circuitization pattern on the surface of the package. The remaining photoresist is then stripped, leaving a thick copper plated circuitization pattern and a thin multilayer background of a seed copper-chromium adhesion layer.
The seed copper can be etched by various methods known in the art. The chromium adhesion layer is removed, for example, by etching with an etchant such as permanganate etches and/or chloride etches. However, these etchants require careful cleaning steps to removed permanganate or chloride entrapped within crevices. Permanganate and hydrochloric acid so entrapped and/or entrained can result in loss of adhesion long after fabrication. This is especially so in the case of subsequent application of gold thin films plated atop the copper circuitization.
Although the above described process is additive, subtractive processes can also be used to create metallized circuits. However, in order to achieve reduction in size of both circuitry lines and sites of interconnections for external components and yet have sufficient thicknesses for carrying current (i.e., high aspect ratios), the industry has preferentially utilized the known processes of additive and semi-additive feature construction.
These techniques, as opposed to subtractive construction, do not require etching of thick copper layers with the concomitant problems of waste and undercutting of the circuitry and features on the substrate surface. This latter detriment requires initial dimensions to be larger than specified for the final package and limits the distance between features. Therefore, the additive process and semi-additive process are preferred.
However, even using either a semiadditive or additive process, undesirable effects remain. In particular, by the very nature of the standard additive/semiadditive processes, selective gold plating of the features is usually a multi-step process that typically requires use of a first and second photoresist, wherein the first photoresist is used to define the electronic features. After this has been achieved, the first photoresist is removed and a second photoresist is utilized to provide at least a portion of the features with a precious metal overcoating. The placement of the second photoresist is crucial to obtain useful product; but, in fact, this alignment is very difficult to achieve. Even when alignment is achieved, the process of plating precious metals onto the exposed upper surface of the interconnections can be problematical. Seepage of the gold plating formulation down the sidewalls of the interconnections, between the sidewalls and the photoresist, can cause underplating of the remaining photoresist sections residing on the seed or thin foil layer and potential lifting of these resist sections from the substrate. When lifting occurs, there is potential to create unwanted plating between features causing them to be electrically shorted or near shorted.
An example of selective plating of two metals, one on top of the other, using two negative photoresists in a additive process, can be found in U.S. Pat. No. 4,866,008 issued to K. Brighton et al. entitled xe2x80x9cMethods For Forming Self-aligned Conductive Pillars On Interconnectsxe2x80x9d (hereinafter referred to as ""008). This patent teaches a process for metal plating on a semiconductor substrate employing a complex multistep process that consists of:
a) application of a uniform seed layer to the surface of the semiconductor substrate;
b) applying, imaging, and developing a negative working mask (photoresist) residing on the seed layer;
c) additively plating a conductive metal into first openings of the developed mask to create metal interconnects of a height that is less than the height of the first mask and the interconnect has a long and short side;
d) applying a second mask to cover the first mask and the metal interconnects, therefore the second mask is not planar;
e) imaging and developing the second mask to create second openings over portions of the metal interconnects, these openings having an essentially rectangular shape with a first dimension comparable to the length of the short side of the first opening and a second dimension that is slightly larger than the length of short side of the first opening, and these second openings define a pillar after additively plating a second metal;
f) the pillars described in (e) have essentially two pair of opposing sidewalls, one opposing pair consisting of the remaining unfilled first mask, while the second pair of opposing sidewalls consisting of the second mask;
g) plating the second metal to form the pillars on portion of the top surface of the interconnect base;
h) stripping the two masks and exposed seed layer; and
i) applying a cladding layer on the exposed top and sidewall surfaces of the pillar and interconnect base.
The ""008 patent differs from the present invention in a number of critical areas, examples include, the substrate in ""008 is a semiconductive material, the first plating in ""008 intentionally does not reach the height of the first mask, the second mask in ""008 is not applied in a planar fashion, and the second mask in ""008 creates openings that are over only a portion of any given underlying element (interconnect).
Another prior art method uses a permanent solder mask also as a gold mask. In this case the process is restricted to using electroless nickel/immersion gold processing, which produces an undesirable brittle interface at the nickel layer. The permanent solder mask also covers the outer edge of the component to be gold plated and therefore the gold if plating performed from this prior art process does not completely cover the topmost portion of the component.
A third prior art method involves stripping the first photoresist layer and re-applying a photoresist material for the purpose of separately defining the gold patterning. This method requires the use of a commoning bar or commoning layer to electrically connect the desired features that are to be plated. Several significant disadvantages are found when employing this method. They include; accurate alignment to the previously defined circuit pattern; penetration of the plating solution under the edges of the resist; and in the case where a seed layer is employed, removal or etch of the seed layer between the features to be plated (otherwise the areas between the features will also be plated thereby shorting the features). In this alternative prior art process flow, all conductive surfaces not to be plated must be cleared or masked prior to plating. Processes of this type also produce plating of the precious metal not only on the topmost surface of the feature but also unnecessarily on their sidewalls as well.
As already noted the electroplating of precious metals requires that all sites to be plated must be electrically connected to the plating bath. Typically, this requires a feature known as a commoning bar from which all other features must be electrically connected. These connections and commoning bar serve no useful function after processing. Between the commoning bar and these connections, much valuable xe2x80x9creal estatexe2x80x9d is made unavailable for product useful features (e.g., pin arrays and ball grid arrays). Additionally, plating then occurs not only on the desired features but also on the circuitry to the buss and the busses themselves. This additional plating area slows the plating process and wastes expensive raw materials which must then be reclaimed. Also, commoning bars often need to be disconnected from the product circuitry through additional etching and/or excising operations, thereby adding unneccessary production steps with the potential for yield loss and certain increase in manufacturing time and cost.
In electroplating, the resulting nickel/gold plating thicknesses are determined in part by the surface area being plated, dwell time in nickel/gold plating baths, and the current applied to the anodes. Therefore, in a conveyorized plating system, the thickness requirements of the product determine the speed at which the plating system can operate. By plating areas not required, the process has less latitude to either increase the thickness range achievable in the process, or increase the speed and throughput for a product at a given thickness specification.
To summarize the prior art status, nickel/gold plating to support wire bonding in BGA packages is applied to all of the circuitry (e.g., signal lines and ground/voltage planes) both front and back, after copper plating has been completed. However, nickel/gold plating is needed only on the upper surfaces of wire bond pads and BGA pads to facilitate wire bonding and ball reflow and therefore such processes are costly due to plating of valuable precious metals in areas where they are not required. Furthermore, the prior art processes suffer from a tendency to have resist lifting and consequent short/near short defects due to underplating which occurs in the nickel/gold plating operation. Considerable scrap results when this occurs with the concommitant loss of valuable raw materials.
Having described the current state of the art and associated problems that still remain, it is an object of the present invention to provide a printed wiring board that has high density microcircuitry and metallized features.
It is an object of the present invention to provide a method of forming a high density printed wiring board that may be single or double sided with metallized elements comprising circuitry, features, lands or pads and furthermore may be multilayered and have embedded circuitry.
It is another object of the present invention to provide a process and article therefrom that has minimal electrical shorting due to lifting of the photoresist during precious metal plating.
It is another object of the present invention to provide a simplified process for overplating at least a portion of the total number of metallized elements on a flexible support.
It is another object of the invention to selectively plate only the topmost surfaces of the metal lands or pads without wasteful plating in unwanted areas such as the sidewalls.
It is a further object of the present invention to provide a printed wiring board having precious metal overplated metallized lands that have high-quality bonding surface.
It is yet another object of the invention to exclusively overplate essentially the entire top surfaces of a portion of the lands on a flexible support, without significantly overplating the circuitry or features elements.
It is still another object of the present invention to provide a method of forming a printed wiring board having the beneficial properties derived from electrolytic plating noble metals without the need for a commoning bar.
The current invention encompasses a process for manufacturing microelectronic elements and microcircuitry lines for printing wiring boards having lands or pads for attachment of semiconductor chips. In particular, the process allows for selectively overplating the lands with at least one noble or precious metal. The overplating process in the current invention is performed without the need for conventional buss or commoning bars and the ancillary circuitry necessary between the lands and the bars in order to perform the overplating. In the current invention the plating circuitry is overplated with a precious metal by using an electrically conductive seed layer in combination with a unique series of steps involving at least two photoresist layers and employing an additive or semiadditive plating methodology. Using the seed layer and the photoresist layers in the manner described in detail below, it is possible to manufacture a flexible printed wiring board having certain lands non-conformally but essentially completely overplated on their topmost surfaces while having other elements such as circuit lines and other features essentially unplated.